The present invention generally relates to semiconductor integrated circuits, and more particularly, to the structure and formation of liner structures that create insulation and diffusion barriers of a tungsten metal contact.
An integrated circuit (IC) generally includes a semiconductor substrate in which a number of device regions are formed by diffusion or ion implantation of suitable dopants. This substrate usually involves a passivating and an insulating layer required to form different device regions. The total thickness of these layers is usually less than one micron. Openings through these layers (called vias or contact holes) allow electrical contact to be made selectively to the underlying device regions. A conducting material is used to fill these holes, which then make contact to semiconductor devices.
In its simplest form, a via may be formed by first masking an insulating layer, e.g., a dielectric layer, with photoresist and then selectively etching a portion of the insulating layer. The via is etched through an opening formed in the photoresist using well known photolithographic techniques, to form an opening to the underlying conductive layer. Depending on the aspect ratio and the interconnection ground rules, isotropic or anisotropic etching processes may be used to form a hole in the dielectric.
After the via etch, and photoresist removal, it is possible to deposit a conductive layer in the via. Conductive material is deposited in the via to form the electrical interconnect between the conducting layers. However, a liner layer is usually desirable between the insulating and conductive layers.
The presence of a liner layer on the sidewalls of the via is desirable because structural delamination and conductor metal diffusion can occur unless there is a layer of protection, a liner layer, between the conductive layer and the etched insulating layer. For structural integrity, the liner layer should line the entire side wall and will generally cover the bottom of the via as well.
The liner and conductive layers may be deposited by sputtering, CVD, electroless deposition and electrodeposition. Rf bias sputtering, in general, is known in the art and involves the reemission of material during the sputter deposition thereof through the effects of attendant ion bombardment of the layer being deposited. In effect, Rf biased sputtering is the positive ion bombardment of a substrate or film during its deposition. Therefore, during Rf bias sputtering, there is always simultaneous etching and deposition of the material being deposited. Previously deposited layers are not etched as part of a standard Rf biased sputter deposition.
High quality contacts are essential to high device yield and reliability, but fabrication of these high quality contacts poses several technical challenges. For example, the contacts are designed to have a high ratio of the height to the diameter, known as the aspect ratio. High aspect ratio is a consequence of several constraints in the design of the IC.
For example, it is desirable to achieve a high packing density of the contacts to enable high circuit density. This constrains the diameter of the contacts to be as small as possible. In addition, the dielectric separating the semiconductor devices from the first metal level must be thick enough to protect transistors. The contacts often span the thickness of dielectric over a transistor and transistor gate over the substrate. These constraints lead to contacts with aspect ratios large enough to present manufacturing challenges.
As integrated circuit technology become smaller, the large aspect ratio combined with very small geometries creates many manufacturing and performance issues. Current attempts to manufacture very small contacts have been plagued with very high resistance. These contact resistances can dominate integrated circuit performance particularly with small process geometries such as thirty-two nanometers.
The dielectrics used for the insulating layers are typically comprised of silicon dioxide, a thermosetting polyarylene resin, an organosilicate glass such as a carbon-doped oxide (SiCOH), or any other type of hybrid related dielectric.
The liner can be a single layer or multiple layers and is not located on the bottom horizontal surface of the via. The liner is comprised of a metal such as, for example, Ta, Ti, Ru, Ir, Co, and W, and/or a metal nitride such as TaN, TiN, and WN. An optional adhesion layer, not specifically shown, can be used to enhance the bonding of the liner to the dielectric layer.
Current processes for depositing the liner generally include a two-step process, which includes a first step of depositing a metal followed by a second step of depositing a metal nitride layer. The two step process for depositing two metal layers is inherently inefficient since it is a two-step process and affects throughput. Moreover, because two layers are deposited, thickness control becomes an issue especially as device dimensions shrink. For example, for 32 nm node device fabrication, the thickness of each layer defining the liner layer is on the order of about 20 Angstroms (Å) for a total thickness of about 40 Å. Smaller thicknesses will be required for future device fabrication, which will be difficult given the relatively high deposition rates utilized to produce individual layer thicknesses at or less than 20 Å.